Job Description
As Senior ASIC Physical Design Engineer, the professional converts RTL designs into GDSII layouts through floorplanning, place and route, and timing closure for Tensor Processing Unit chips. These chips power AI applications, benefiting engineers with accelerated AI workloads on custom silicon. The process incorporates Python, Tcl, or Perl scripts for automation and integration.
Google designs AI hardware solutions at hyperscale, serving Google Cloud customers and global users with custom silicon. The company develops Tensor Processing Units for machine learning models in data centers. Google's infrastructure team ensures efficiency and reliability for billions of users.
Work involves participating in physical design from RTL to GDSII, collaborating with DFT, floorplan, and signoff teams. Engineers conduct feasibility studies for microarchitectures, optimize runs with Synopsys or Cadence tools, and handle LEC, PI/SI, DRC/LVS checks. Interactions occur with RTL teams for block closure. A challenge includes managing performance, power, and area trade-offs in full-chip designs.
The US base salary range is $156,000-$229,000, including bonus and equity. Full-time positions feature benefits such as health programs and learning platforms. Roles support remote arrangements in the US.
Responsibilities
- Participate in the Physical Design of complex blocks
- Contribute to the design and closure of the full chip and individual blocks from RTL-to-GDS
- Collaborate with internal logic and internal and external teams to achieve the best Power/Performance Analysis (PPA). This includes conducting feasibility studies for new microarchitectures as well as optimizing runs for finished RTL
Requirements
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience
- 7 years of experience with physical design (e.g. from RTL to GDSII, including key stages like floorplanning, place and route, and timing closure)
- Experience in Python, Tcl, or Perl scripting
- Experience working with external partners on Physical Design (PD) closure
- Experience in Static Timing Analysis (STA), with an understanding of how to define timing corners, margins and derates
- Experience with Synopsys/Cadence PnR tools
- Experience with backend flows (e.g., LEC, PI/SI, DRC/LVS, etc.).
- Understanding of DFT including Scan, MBIST and LBIST
- Understanding of performance, power and area (PPA) trade-offs