Job Description
The position drives SoC architecture for memory subsystems in Samsung Research America, targeting next-generation Galaxy devices. This involves crafting Fabric, System cache, and DRAM controller proposals to enhance performance on benchmarks and applications. The architect communicates results across hardware, software, and leadership teams, validating via simulation and collaboration with silicon engineers.
Samsung Research America partners with strategic groups to innovate core IP for smartphones and tablets worldwide. The team defines high-performance SoC elements, influencing products like Galaxy flagships through global collaborations.
Work includes guiding innovative Fabric and System cache features, evaluating benefits, performing high-level modeling, and directing simulation studies. Collaborations span onboard teams for debugging and proposals to design teams using detailed documentation. Team members interact with silicon teams to verify features and ensure SOC Driver OS integrations. A constraint is balancing area, power, and latency tradeoffs in complex architectures using ARM buses and JEDEC standards like LPDDR and DDR.
Compensation ranges from $158,800 to $218,100 USD annually based on factors like experience and location. The role is office-based, involving sitting and standing at desks, in-person and phone communication, and operating computers and telephones. It offers annual bonuses, equity, and comprehensive benefits including health programs.
Responsibilities
- Guide development of Fabric System cache and DRAM controller features
- Identify architecture proposals for targeted workloads
- Evaluate benefits and communicate across engineering audiences
- Perform high-level performance modeling and analysis
- Direct performance modeling and studies
- Deliver proposals and specifications to design teams
- Collaborate with silicon teams for verification and debugging
- Work on cross-team integrations across SOC Driver OS and System
- Maintain performance standards in SOC collaborations
Requirements
- BSc Master's or PhD in Computer Science Engineering or equivalent
- 3+ years experience in SOC or ASIC design and architecture
- Knowledge of Fabric NoC System Cache DRAM controller
- Understanding of memory controller architecture scheduling and QoS
- Familiarity with ARM bus infrastructure like ACE AXI AHB
- Knowledge of JEDEC standards such as LPDDR DDR or HBM’s
- Background in memory systems and computer architecture
- Experience with BookSim Simulator preferred
- Experience with Platform Architect preferred